This kind of switching transistor driver circuit is disclosed in Japanese Patent Laid-Open No. 4-230117. The circuit is configured as shown in FIG. 15.
In this configuration, when a load 230 is driven by a high voltage power supply 228, voltage is applied from the high voltage power supply 228 to a series circuit of a pair of power N-channel MOS transistors (hereinafter, will be referred to as transistors) 224 and 225, and the load 230 is connected to a junction point of the source of the transistor 224 and the drain of the transistor 225. Of the transistors 224 and 225, the transistor 224 on the high potential side is turned on/off by a pulse signal having a different reference potential from a low voltage circuit. Reference numeral 229 denotes a low voltage power supply.
Thus a rising edge serving as a leading edge of a pulse signal inputted for driving the transistor 224 on the high potential side and a falling edge serving as a trailing edge of the pulse signal are detected, the reference potential of each edge detection pulse is level shifted, and then an RS flip-flop 222 is set/reset by each edge detection pulse, so that a pulse equivalent to the inputted pulse is generated according to the reference potential of the transistor 224 to control the on/off of the transistor 224.
In this configuration, the driver circuit of the transistors 224 and 225 is constructed in a semiconductor integrated circuit 200. In the semiconductor integrated circuit 200, reference character VS denotes a lower reference potential input terminal of the transistor 224, reference character VB denotes an upper reference potential input terminal of the circuit for driving the transistor 224, reference characters VDD and VCC denote power supply input terminals, reference characters VSS and COM denote ground terminals, reference character HO denotes a high side output terminal fed with the gate signal of the transistor 224. Reference character LO denotes a low side output terminal fed with the gate signal of the transistor 225. Reference character HIN denotes a high side input terminal and reference character LIN denotes a low side input terminal. Output pulse signals are outputted from the high side output terminal HO and the low side output terminal LO in response to the input pulse signals from the high side input terminal HIN and the low side input terminal LIN to control the on/off of the transistors 224 and 225.
In logic where the transistors 224 and 225 are simultaneously turned on and through current does not pass between the high voltage power supply 228 and the ground, the input pulse signals are inputted from the high side input terminal HIN and the low side input terminal LIN. Upon switching of input logic from the high side input terminal HIN and the low side input terminal LIN, a period called a dead time is set in which the high side input terminal HIN and the low side input terminal LIN are both inevitably set at “L” level and the high side output terminal HO and the low side output terminal LO are both set at “L” level.
The input pulse signals of the high side input terminal HIN, the low side input terminal LIN, and an input terminal SD are configured such that when the input terminal SD is set at “H” level, the outputs of latches 204 and 205 are set at “H” level, the outputs of NOR gates 206 and 207 are set at “L” level, the high side output terminal HO and the low side output terminal LO are set at “L” level, and no signals are transmitted from the high side input terminal HIN and the low side input terminal LIN to the high side output terminal HO and the low side output terminal LO. When inputting “H” level to the input terminal SD upon initialization or the like, the latches 204 and 205 are initialized and the high side output terminal HO and the low side output terminal LO are set at “L” level. When performing a normal operation, “L” level is inputted to the input terminal SD, so that pulse signals from the high side input terminal HIN and the low side input terminal LIN are respectively outputted from the NOR gates 206 and 207. In VDD/VCC level shifts 208 and 209, a pulse signal using VDD as a power supply voltage reference is transformed to a pulse signal using VCC as a power supply voltage reference.
The signal from the VDD/VCC level shift 209 is transmitted to the gates of output N-channel MOS transistors 212 and 213 via a delay circuit 210 for matching a delay time from the low side input terminal LIN to the low side output terminal LO with a delay time from the high side input terminal HIN to the high side output terminal HO, and the transistor 225 is driven by the signal from the low side output terminal LO. When a VCC power supply voltage is lower than a predetermined voltage in an undervoltage detection circuit 231, the circuit may not normally operate. Thus the undervoltage detection circuit 231 is configured such that the signal from the low side input terminal LIN is not transmitted to the gates of the output N-channel MOS transistors 212 and 213 and the signal from the high side-input terminal HIN is not transmitted to the gates of transistors 220 and 221.
The signal from the VDD/VCC level shift 208 is transformed, in a pulse oscillator 214, into two thin pulses in which the leading edge and the trailing edge of an input waveform are detected. The two pulses are respectively inputted to the gates of high breakdown voltage transistors 215 and 216 for level shift and the voltage levels of the pulses are changed. Thereafter, the pulses pass through a pulse filter 219 and are inputted to the set input terminal and the reset input terminal of the RS flip-flop 222. The input pulse signal from the high side input terminal HIN is outputted to the high side output terminal HO while the voltage level of the signal is changed (in reality, there is a slight time lag), so that the transistor 224 is driven.
The voltage of the low voltage power supply 229 is always inputted to the VCC terminal. When the low side output terminal LO is set at “H” level and the high side output terminal HO is set at “L” level, a voltage obtained by subtracting the diode voltage of a diode 227 from the voltage of the low voltage power supply 229 is applied to the upper reference potential input terminal VB. When the low side output terminal LO is set at “L” level and the high side output terminal HO is set at “H” level, a voltage close to the voltage of the high voltage power supply 228 is applied to the lower reference potential input terminal VS. The voltage of the upper reference potential input terminal VB increases in parallel with the voltage of the lower reference potential input terminal VS while keeping, in a capacitor 226, the voltage obtained by subtracting the diode voltage of the diode 227 from the voltage of the low voltage power supply 229.
In a mode where a potential difference between the upper reference potential input terminal VB and the lower reference potential input terminal VS is lower than a predetermined voltage in an undervoltage detection circuit 223, the circuit may not normally operate. Thus the signal from the high side input terminal HIN is not transmitted to the gates of the transistors 220 and 221.
FIG. 16 shows a specific structural example of the pulse oscillator 214 serving as a constituent element of FIG. 15. The circuit operations will be described below with reference to the timing chart of FIG. 17.
Reference numerals 141, 143, 144, 145, 146, 147, 148, 149, 150 and 151 denote inverters, reference numerals 142 and 152 denote NOR gates, reference numerals 153, 154, 155 and 156 denote capacitors, reference numerals 157, 158, 159, 160 and 161 denote signal lines, reference numeral 157 denotes an input signal from the VDD/VCC level shift 208 of FIG. 15, reference numeral 159 denotes an output signal to the gate of the transistor 215, and reference numeral 161 denotes an output signal to the gate of the transistor 216.
In FIG. 17, (t153+t154) represents an amount of delay caused by the capacitors 153 and 154 of FIG. 16 and (t115+t156) represents an amount of delay caused by the capacitors 155 and 156 of FIG. 16.
The signal level-shifted by the VDD/VCC level shift 208 is inputted from the high side input terminal HIN to the signal line 157 serving as the input of the pulse oscillator 214, a signal obtained by delaying the signal of the signal line 157 is outputted to the output (the signal line 158) of the inverter 146, and a signal obtained by delaying and inverting the signal of the signal line 157 is outputted to the output (the signal line 160) of the inverter 151. Thus the thin pulse where the leading edge of the signal of the signal line 157 has been detected is outputted to the output (the signal line 159) of the NOR gate 142, the thin pulse where the trailing edge of the signal of the signal line 157 has been detected is outputted to the output (the signal line 161) of the NOR gate 152, the signal of the output (the signal line 159) of the NOR gate 142 is inputted to the inverted set input terminal of the RS flip-flop 222 via the high-voltage level shift circuit and the pulse filter 219 of FIG. 15, and the signal of the output (the signal line 161) of the NOR gate 152 is inputted to the inverted reset input terminal of the RS flip-flop 222 via the high voltage level shift circuit and the pulse filter 219.
The two set and reset pulse filters 219 are provided as constituent elements of FIG. 15. FIG. 18 shows a specific configuration example showing one of the two pulse filters 219. The circuit operations will be described below with reference to the timing chart of FIG. 19.
Reference numeral 215 denotes a high breakdown voltage transistor for level shift, reference numerals 217 and 241 denote resistors, reference numeral 244 denotes a ballast resistor, reference numeral 243 denotes a parasitic capacitance present on diffusion as a semiconductor between the drain and ground terminal of the transistor 215, reference numerals 233, 234, 235 and 236 denote P-channel MOS transistors, reference numerals 237, 238, 239 and 240 denote N-channel MOS transistors, and reference numeral 242 denotes a capacitor.
Waveform A in FIG. 19 corresponds to the waveform of the output (the signal line 159) of the NOR gate 142 shown in FIG. 16. Waveform B is rounded by the influence of the resistor 217 and the capacitor 243, waveform C is slightly made angular, and waveform D is further sharpened. In waveform E, charging to the capacitor 242 through the resistor 241 is made longer and thus the rising time is delayed. Waveform F is made angular, has a leading edge delayed from the leading edge of the waveform A, and has a pulse width shorter than that of the waveform A. However, the pulse is normally inputted to the inverted set input terminal of the RS flip-flop 222.
The pulse filter 219 of FIG. 15 has the following effect: even when noise is inputted to the previous stage of the pulse filter 219 due to dv/dt transient phenomena or the like, the noise is removed in the waveform F by filter effect as indicated by the dotted line waveforms of FIG. 19. Thus the noise is not inputted to the RS flip-flop 222.
As described above, in the conventional switching transistor driver circuit, the pulse filter 219 (specifically shown in FIG. 18) is disposed between the high voltage level shift circuit and the RS flip-flop 222, and thus even when noise having a short pulse width occurs in the previous stage of the RS flip-flop 222 due to dv/dt transient phenomena or the like, the noise is not inputted to the RS flip-flop 222. Thus no malfunctions occur.